This invention relates in general to the field of computer architecture, and more specifically to a coprocessor interface for communicating between a central processor and one or more co-processing devices.
Early microprocessor based systems utilized a central processing unit, or CPU, which executed instructions, one at a time, in the order in which they were presented. These CPU""s, due to their relative complexity, and associated cost, were typically designed to have universal application. That is, they were designed as general purpose CPU""s.
As the use of general purpose CPU""s increased, so did the variety of programs they were called on to execute. In some instances, certain programs ran extremely slow because they required the CPU to perform complex calculations that were really beyond the scope of what it was intended to perform. An example of such calculations included floating point operations, such a multiply, divide, etc.
To assist the CPU in executing such complex calculations, a floating point coprocessor was designed. The floating point coprocessor was essentially a second processor, external to the CPU, that was designed to perform certain complex operations such as a floating point multiply, a floating point divide, etc, albeit much faster than the CPU. In operation, the CPU, when it was asked to perform a complex operation, would pass the operation over to the floating point coprocessor. The coprocessor would complete the task, and pass the results back to the CPU.
Although the development of the floating point coprocessor enhanced the processing speed of certain applications, its cost kept it from being added to all systems. So, many computer systems were designed around a particular CPU (e.g., an 80286), and were designed to accommodate a dedicated floating point coprocessor (e.g., an 80287), but the coprocessor was not provided with the system. If a user of the system executed the types of applications that could take advantage of the coprocessor, for an additional cost, s/he could add the coprocessor to the system.
Thus, while development of the coprocessor enhanced the performance of many CPU based systems, certain design problems arose. The first is that the coprocessor and the general purpose CPU must be tightly integrated, or designed together, to allow them to communicate together effectively. Operationally speaking, the CPU must be able to detect when a program wishes to use the coprocessor, it must pass those instructions over to the coprocessor, it must provide the data to the coprocessor that corresponds to the instructions, and it must be able to receive results back from the coprocessor. In addition, the coprocessor must know whether the CPU has been interrupted by another process, and whether it still requires the result that it is calculating. One skilled in the art will appreciate that many other issues arise relating to the communication that must occur between a CPU and a coprocessor. So, since the CPU and the coprocessor have to be so tightly integrated, most coprocessors that have been designed are typically designed to work with a particular CPU.
A resulting problem that emanates from the tight integration that is required between a CPU and coprocessor is that enhancement in the design of a particular CPU often requires an enhancement (or change) in the design of its associated coprocessor. That is, an older coprocessor will typically not function with a newer CPU, and a newer coprocessor will typically not function with an older CPU. Thus, every time a CPU manufacturer wishes to introduce a new CPU, they must decide whether they want to develop a dedicated coprocessor that will work along with it. A decision to develop a coprocessor is a very costly decision that ultimately must be supported by the marketplace.
In addition, although the above-described history of the floating-point coprocessor provides a basis for understanding that the coprocessor must be designed with a specific CPU in mind, it does not tell the whole story. Modern applications often require complex, time-consuming calculations that are not appropriate either for a CPU, or for a floating-point coprocessor. That is, other types of coprocessor""s are required in certain applications, for optimized performance. Such applications include 3-D rendering for graphics applications, audio/signal processing etc. But, graphics coprocessors, audio coprocessors, etc. have to be designed with a particular interface, e.g., AGP, and typically only operate with CPU""s that are designed for that interface.
From the viewpoint of a system designer, the task of choosing a particular CPU for a particular task is increasingly difficult. The designer must anticipate the future needs of the system, utilizing existing CPU and coprocessor designs, without being able to select the CPU and its coprocessors separate from one another. That is, a designer may have an application that may be satisfied by a relatively simple CPU, but requires a fairly complex graphics coprocessor. Unfortunately, the complex coprocessor is only compatible with an equally complex (and costly) CPU. And, vice versa.
Therefore, what is needed is a configurable coprocessor interface that allows a variety of CPU""s to be easily coupled to a variety of different coprocessors, without requiring that the coprocessors be designed specifically for those CPU""s.
What is also needed is a configurable coprocessor interface that allows both forward and backward compatibility between CPU""s and coprocessors. That is, a coprocessor interface is desired that allows older, or legacy, coprocessors to be utilized with newer CPU""s, and vice versa.
Further, what is needed is a xe2x80x9cstandardizedxe2x80x9d coprocessor interface for which CPU""s and coprocessors can be designed. Such an interface would allow a system designer to select those specific CPU and coprocessor combinations that provide an optimum solution for the designer""s needs, without regard to proprietary interface requirements.
Finally, what is needed is a coprocessor interface that takes advantage of modern processing technology, such as multiple-issue of instructions, out-of-order data transfer, etc., without mandating that such technology exist in every device on the interface.
The present invention provides a scalable and configurable coprocessor interface that distinguishes between instruction types to be transferred between a central processing unit (CPU) and a coprocessor, to allow for sequential or parallel transfer of differing instruction types, to one or more coprocessor pipelines. In addition, the interface provides separate TO/FROM data buses between the CPU and the coprocessor to allow for simultaneous data transfer (in/out) between the CPU and the coprocessor. The interface further provides for disassociation between instructions that are transferred, and data that is transferred, to allow data to be transferred in variable time slots with respect to their associated instructions. Moreover, the interface allows for out-of-order data transfer, without requiring absolute, pre-assigned tags to be associated with each data transfer. Rather, the interface keeps track of the relative order of outstanding instructions that require data for execution, and provides a relative order indicator along with each piece of data as it is transferred. Furthermore, condition code signaling is provided from the coprocessor to allow the coprocessor to evaluate CPU specific conditional instructions, and inform the CPU as to whether it should execute, or not execute, the CPU conditional instructions.
An embodiment of the present invention provides a coprocessor interface between a central processing unit (CPU) and a multi-issue coprocessor. The interface includes an instruction transfer signal group and an issue group designator. The instruction transfer signal group transfers instructions from the CPU to the multi-issue coprocessor. The issue group designator specifies an issue path within the multi-issue coprocessor, for execution of each of the instructions. The multi-issue coprocessor executes each of the instructions within the issue path specified by the issue group designator.
In another aspect, the present invention provides a coprocessor interface within a central processing unit (CPU) for interfacing to one or more issue paths within a coprocessor. The coprocessor interface includes an issue path descriptor and an instruction order signal group. The issue path descriptor is associated with an instruction transfer signal group, and specifies with each instruction transferred to the coprocessor, which of the one or more issue paths within the coprocessor is to execute each instruction. The instruction order signal group indicates to the coprocessor a relative execution order for each instruction transferred to the coprocessor.
In a further aspect, the present invention provides a computer program product for use with a computing device. The computer program product includes a computer usable medium with computer readable program code embodied in the medium, to cause a coprocessor interface to be described. The computer readable program code includes first program code and second program code. The first program code provides an instruction transfer signal group for transferring instructions from a CPU to a multi-issue coprocessor. The second program code provides an issue group designator to specify an issue path within the multi-issue coprocessor, to execute each of the instructions.
In yet another aspect, the present invention provides a computer data signal embodied in a transmission medium. The signal includes computer readable first program code and second program code. The first program code provides an issue path descriptor associated with an instruction transfer signal group for specifying with each instruction transferred to a multi-issue coprocessor, which of one or more issue paths within the multi-issue coprocessor is to execute each instruction. The second program code provides an instruction order signal group, for indicating to the multi-issue coprocessor a relative execution order for each instruction.
In a further aspect, the present invention provides a method for providing coprocessor instructions from a central processing unit (CPU) to a coprocessor having a plurality of issue paths. The method includes designating, along with each of the instructions provided to the coprocessor, which of the plurality of issue paths are to execute each of the instructions; and if two or more instructions are provided to the coprocessor in parallel, indicating an execution order for the two or more instructions.
Other features and advantages of the present invention will become apparent upon study of the remaining portions of the specification and drawings.